1. Field of Invention
The present invention relates to a structure and manufacturing method of a polysilicon load for static random access memory (SRAM). More particularly, the present invention relates to the structure and manufacturing method of a polysilicon load having a high resistance that can be used in a four-transistor SRAM (4T SRAM). In addition, some of the restrictions for miniaturizing memory cells using a conventional method can be eliminated.
2. Description of Related Art
FIG. 1 is a circuit layout diagram of a conventional four-transistor static random access memory (4T SRAM). As shown in FIG. 1, R.sub.1 and R.sub.2 are load resistors, and M.sub.1 and M.sub.2 are enhancement mode NMOS transistors that function as drivers. Furthermore, there are enhancement mode NMOS transistors M.sub.3 and M.sub.4 that are used for accessing data contained in the SRAM. The gates of transistors M.sub.3 and M.sub.4 are controlled by a horizontal conducting line known as a word line (WL). The drain terminals of M.sub.3 and M.sub.4 are connected to transistor drivers M.sub.1 and M.sub.2, respectively. Therefore, the ON and OFF state of the transistors M.sub.1 and M.sub.2 are closely related to the switching states of transistors M.sub.3 and M.sub.4. The source terminals of M.sub.3 and M.sub.4 are each connected to a vertical conducting line known as a bit line (BL).
In general, a high resistance polysilicon line is used as a load resistor in a four-transistor SRAM (4T SRAM). FIG. 2 is a top view of a conventional polysilicon line structure. A conventional polysilicon line is formed by first depositing a polysilicon film, and then adjusting the line resistance through an impurity implant. Subsequently, microlithographic and etching processes are used to obtain the necessary polysilicon line pattern 20 (including 20a and 20b). Thereafter, portions of line 20a and region within the line boundary 22 is implanted a second time using heavily concentrated impurities. The twice-implanted region becomes a connector 22a region and that the second implant is for lowering the resistance of the polysilicon line 20a. The remainder portions of the polysilicon line 20 now serves as a polysilicon load 20b. Therefore, resistance of polysilicon load 20b is largely determined by factors such as the quantity of implanted impurities during the first implant, thickness of the polysilicon film, the width W and the length L of the polysilicon load line 20b.
Conventionally, a high polysilicon load resistance can be obtained by methods such as lowering the thickness of polysilicon film, increasing the length of polysilicon load, or reducing the width of the polysilicon load. However, as SRAM cells are miniaturized further, a load having a sufficiently high resistance becomes harder to make using the conventional method described above. The main reason is that during subsequent thermal processing operations, highly concentrated impurities of the second implant within the connector will out-diffuse into the polysilicon load and resulting in a reduction in the final effective length of the polysilicon load. This presents a difficult problem for the conventional method when SRAM cells are further miniaturized in the future. Since the linear dimension of a polysilicon load is incapable of any more extension, and furthermore, reduction of polysilicon line width is still limited by the known processing techniques, therefore, the conventional method of forming a polysilicon load is a major drawback for future dimensional reduction of memory cells.
In light of the foregoing, there is a need in the art to provide an improved structure and manufacturing method for forming a polysilicon load.